[UCI-Calit2] Power and Throughput Issues in Next-Generation Packet Switches

[Anna Lynn Spitzer]

Power and Throughput Issues in Next-Generation Packet Switches 

A Networked Systems Seminar

With Nick Bambos, Stanford University

2-3 p.m.
Thursday, March 6
Calit2 Building, Room 3008

High-speed packet switches achieve increasingly higher throughputs and
better jitter management at the expense, however, of substantial
increase in utilized power. The latter has become an acute problem, as
higher power results in unacceptable thermal stress of switching
chips/systems and requires extensive cooling apparatus. Low power
circuit design is one way to partially address the problem. Instead, in
this talk Bambos focuses on operational and algorithmic methods for
power managing switches. 
He will present some recent results for power-aware packet scheduling in
packet switches, focusing on the power vs. latency tradeoff and
discussing how to systematically manage power/speed modes against
acceptable packet delays and traffic bursts. The power management
algorithms are also aligned with the need to achieve maximal throughput
when the traffic load becomes excessive. 

 
About the Speaker:

Nick Bambos is a professor at Stanford University, with a joint
appointment in the Department of Electrical Engineering and the
Department of Management Science. He received his Ph.D. in electrical
engineering from UC Berkeley in 1989. He has received various awards,
including the NSF young investigator award, the Cisco Systems Chair at
Stanford and the IBM faculty award. His current research interests
include high-performance engineering of computer systems/networks;
data-center computing; wireless computing/networking; media streaming
over wireless; and low power design.  

For more information, contact Athina Markopoulou, athina at uci.edu