[CPCC] REMINDER: SEMINAR: Adaptive Analog Equalization for Multimode Fiber 10/12 10AM

Ender Ayanoglu ayanoglu at uci.edu
Sun Oct 11 17:46:50 PDT 2009


                                  SEMINAR


          Adaptive Analog Equalization of Multimode Fiber Channels
                     Using 0.13um CMOS Technology

                                    by

                              Mahyar Kargar

                         October 12, 2009, Monday
                                  10 AM
                          2430 Engineering Hall
                            (Colloquium Room)


                                 ABSTRACT

An adaptive analog high-speed decision feedback equalizer (DFE) to
combat the inter-symbol interference (ISI) caused mainly by modal
dispersion in multimode optical fiber (MMF) channels has been realized
in 0.13um CMOS.  Based on simulation results from MATLAB, a 3-tap
fractionally spaced feedforward filter and a 3-tap adaptive feedback
filter showed enough equalization capability to compensate for up to
300 m of legacy MMF. The DFE chip consists of a 3-tap T/2-spaced
feedforward filter, used to cancel the pre-cursor ISI, and a 3-tap
T-spaced feedback filter used to cancel the post-cursor ISI. A novel
modified Cherry-Hooper stage is designed as the delay element in the
feedforward path. A Delay-Locked Loop (DLL) plus a gain-control loop
are also realized to control the delay and gain of each delay element
in the feedforward path respectively. A slicer incorporating
high-speed CML structure with inductive peaking as bandwidth
enhancement technique is realized. High-speed CML D Flip-Flops (DFF)
are used as delay elements in the feedback path. The Least Mean-Square
(LMS) algorithm is used to adapt the coefficients in the feedback
path. The DFE output is applied to a 10 Gb/s binary clock and data
recovery (CDR) circuit to extract the clock from slicer output and
providing it to the DFFs. The DFE output data is retimed with the
recovered clock from CDR.  Retimed data and recovered clock are
applied to output 50 Ohm drivers to observe the chip performance. The
adaptive DFE was able to equalize 10Gb/s PRBS data corrupted by 300m
of MMF and 12 inch FR4 trace with measured BER < 1E-13. The measured
10GHz recovered clock had less than 450fs rms random jitter.

                             SPEAKER'S BIOGRAPHY

Mahyar Kargar was born in Tehran, Iran, in 1978. He received the B.S.
degree from Sharif University of Technology, Tehran, Iran in 2001, and
the M.S. degree from the University of Southern California, Los
Angeles, in 2003, all in electrical engineering. He is currently a
Ph.D. candidate at the University of California, Irvine, CA. In June
2005 he joined ClariPhy Communications in Irvine as an analog IC
design intern, From 2007 to 2008 he was a senior analog IC design
engineer at ClariPhy. Since May 2009 he has been with Broadcom
Corporation as a staff electronic design engineer where he is involved
in designing high-speed analog circuits for optical communications.
His research interests are in the areas of high-speed mixed-signal
circuit design, adaptive equalization and data converters. Mr. Kargar
received the CPCC fellowship from UC Irvine in the 2006-2007 and
2007-2008 academic years. He also received the Outstanding M.S.
Graduate Award from the Association of Professors and Scholars of
Iranian Heritage (APSIH) in 2003. He is a student member of the IEEE.


More information about the CPCC mailing list