[CPCC] SEMINAR: Low Power 10 GS/s 5 bit ADC 11/16 Monday 10 AM

Ender Ayanoglu ayanoglu at uci.edu
Mon Nov 9 13:36:51 PST 2009


                                CPCC SEMINAR


          A Low Power 10 GS/s 5 bit ADC in 0.13um CMOS Technology

                                    by

                             Darya Mohtashemi

                         November 16, 2009, Monday
                                  10 AM
                          2430 Engineering Hall
                            (Colloquium Room)

                                 ABSTRACT

In high-speed data communication systems with bit rates of 10Gb/s and
higher, some form of channel equalization is required to ensure error free
data transmission. Digital equalization has been shown to have favorable
performance over more conventional analog techniques, therefore, high-
speed ADCs are becoming fundamental components of high-speed communication
systems. The bottleneck in such systems has been the design of the ADC
with reasonable power dissipation. This talk focuses on the challenges of
designing a low power 10GS/s flash ADC in 0.13um CMOS and the high-speed
design techniques used in the development of this A/D converter.


                            SPEAKER'S BIOGRAPHY

Darya Mohtashemi received the B.S. degree in Electrical Engineering from
K. N. Toosi University of Technology in Tehran, Iran in 2004 and the M.S.
degree in Electrical Engineering from the University of California, Irvine
in 2006. She is currently pursuing  her PhD degree at the University of
California, Irvine. Her research interests include the design of high-
speed analog/mixed-signal integrated circuits for optical communications
with a focus on high-speed ADC design. She has held two summer internships
at ClariPhy Communications Inc. where she was an analog IC design engineer
intern. Ms. Mohtashemi received the UC Irvine Henry Samueli Endowed
Fellowship in 2006. She is a student member of IEEE.




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