[CPCC] TALK: Polymorphic Processor Fri 10/12 1:30 PM

Ender Ayanoglu ayanoglu at uci.edu
Tue Oct 9 16:36:25 PDT 2007


                                  TALK

          The MOLEN Polymorphic Processor and Its Dedicated Toolchain

                            G. N. Gaydadjiev
                        Delft University of Technology

                            October 12, 2007
                                 Friday
                              1:30-2:30 PM
                                 ET 331


                                Abstract

In this talk, a polymorphic computing paradigm is presented. It
incorporates both general purpose and custom computing processing,
allowing for arbitrary on-demand functional extensions in hardware
without the need of any additional ISA extensions.

Three major components are involved in this new approach: programming
paradigm, machine organization, and dedicated toolchain. The MOLEN
programming paradigm is respecting the sequential consistency model
when programming the Custom Computing Machines (CCM).  MOLEN requires
one time ISA extension with four up to seven polymorphic instructions
that offers to the user almost an arbitrary number of CCM
functionalities.

In this processor organization the general purpose (GPP) and the
reconfigurable processors (RP) are tightly coupled. An arbiter directs
the native ISA instructions to the GPP and the polymorphic
instructions to the RP. The RP is composed of a reconfigurable
microcode unit and a custom configured unit (CCU). The software
support for this processor is provided by the Delft Workbench tool
platform. A profiling and cost-estimation suite facilitates the
application partitioning to adequate software and hardware
segments. An optimization and transformation toolbox restructures the
application with respect of the hybrid SW/HW execution. The MOLEN
compiler generates the GPP executable, replacing the hardware segments
with the necessary hardware reconfiguration and invocation
instructions. In addition, the compiler provides optimal scheduling of
the hardware reconfiguration that hides the reconfiguration
latency. The DWARV toolset translates the hardware segments into VHDL
designs, which are later configured as MOLEN CCUs.


                       Speaker's Biography

Georgi Gaydadjiev is currently an assistant professor in the Computer
Engineering Laboratory, Delft University of Technology, The
Netherlands. His research and developmentexperience includes 15 years
in hardware andsoftware design at System Engineering Ltd. in Pravetz,
Bulgaria, and Pijnenburg Microelectronicsand Software B.V. in Vught,
The Netherlands.

His research interests include embedded systems design, advanced
computer architectures, hardware/software codesign, VLSI design,
cryptographic systems, and computer systems testing.

He is a member of the IEEE and the IEEE Computer Society.

Host: Prof. Fadi Kurdahi



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