[UCI-Calit2] CS Seminar Series-Friday April 19

[Anna Lynn Spitzer]

Computer Science Seminar Series

Title: 		Looking "Up" for Technology Scaling

Speaker: 	Puneet Gupta, UCLA Department of Electrical Engineering

Time		11 a.m.-noon

Date: 		Friday April 19

Location: 	Donald Bren Hall, Room 6011


Abstract:
Scaling of physical dimensions faster than the optical wavelengths or
equipment tolerances used in the manufacturing line has led to increased
process variability and low yields, making manufacturing expensive and
design unpredictable. "Equivalent scaling" improvements, perhaps as much
as one full technology generation, can come from looking "up" to circuit
design and even to software (operating systems, compilers and
applications).

In first half of the talk, Gupta will discuss design-assisted technology
scaling. With few examples from lithographic patterning and mask flows,
he will illustrate how design information can be leveraged practically
to radically reduce pessimism inherent in semiconductor manufacturing,
as well as guide process research and development.

In the second half of the talk, he speculatively argues for
underdesigned and opportunistic computing machines, which offload some
of the variability handling burden to higher layers in the
hardware-software stack. Gupta will use examples to show that a fluid
hardware-software interface can result in substantial improvements in
power, yield and application quality.

Bio:

Gupta (http://nanocad.ee.ucla.edu) received the B.Tech degree in
electrical engineering from the Indian Institute of Technology, Delhi in
2000, and a Ph.D. in 2007 from the University of California, San Diego.
He co-founded Blaze DFM Inc. (acquired by Tela Inc.) in 2004 and served
as its product architect till 2007.

He has authored more than 100 papers, 16 U.S. patents, a book and a book
chapter. He is a recipient of an NSF CAREER award, IBM Faculty Award,
ACM/SIGDA Outstanding New Faculty Award, European Design Automation
Association Outstanding Dissertation Award and SRC Inventor Recognition
Award. Gupta has given tutorial talks at DAC, ICCAD, Intl. Conference on
Microelectronic Test Structures, SPIE Advanced Lithography Symposium,
and served as program chair of the IEEE DFM&Y Workshop in 2009, 2010 and
2011. He currently leads the multi-university IMPACT+ Center
(http://impact.ee.ucla.edu), which looks at design and process
challenges for future semiconductor technologies.

Gupta's research has focused on building high-value bridges across
application-architecture-implementation-fabrication interfaces for
lowered cost and power, increased yield and improved predictability of
integrated circuits and systems.