[CPCC] SEMINAR: Multicore Simulator using NoC 11/30 Monday 10 AM

Ender Ayanoglu ayanoglu at uci.edu
Wed Nov 25 14:15:51 PST 2009


[Note location change for this seminar.]


                               CPCC SEMINAR

      Fast and Scalable Simulator of a Multicore using Network-on-Chip

                                   by

                              Jungsook Yang

                       November 30, 2009, Monday
                                 10 AM
                        Engineering Gateway 3161

                                ABSTRACT

The multi-core system-on-chip architectures that use billions of
transistors require a more scalable and reusable on-chip interconnect
method. Network-on-Chip (NoC) is on-chip packet switched network
architecture with a regular topology which provides a homogeneous
communication environment for the Intellectual Property (IP) cores. As
it is a scalable communication platform, it can also integrate more
cores achieving higher computational capacity. However, harnessing the
multicores on NoC poses serious complexity challenges in exploring
optimal hardware configuration and application mapping solutions. In
this presentation, we will present the scalable simulator of multicore
architecture with network-on-chip which can help explore design space
fast and efficiently. We also will present a ray tracing application
case study and show the importance of our multicore NoC architecture
simulator as a parallel algorithm development and verification
platform.

                            SPEAKER'S BIOGRAPHY

Jung Sook Yang received her B.S. degree from Korea Advanced Institute
of Science and Technology (KAIST), Daejon, Korea and is currently
working toward the Ph.D degree in Electrical Engineering and Computer
Science at University of California, Irvine. Her research interests
are in parallel software development and application mapping for
network-on-chip multicore systems.


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